SOC Engineering, Sr Staff Engineer - 18079

Job Description and Requirements

Alternate Job Title:

• SoC Verification Technical Lead

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of SoC verification, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a verification plan you wrote in week two. You know that verification is not just about coverage numbers, it is about understanding what can actually break in silicon and making sure it does not.

Leading a team does not mean delegating and disappearing. You are in the weaveform debugger alongside your engineers when a protocol violation shows up at 2am, and you can spot a gap in a testbench architecture during a design review without needing to see the code. You have learned to read a customer's SOC spec and immediately know where the risk lives, whether it is in the interconnect, the power domain crossings, or that custom accelerator block nobody wants to talk about yet.

You do not wait for perfect requirements. You ask the right questions, build a verification plan that actually maps to what can go wrong, and adjust as the design evolves. At Synopsys, you will work directly with customers building chips for AI, automotive, aerospace, and high-performance computing, and the verification strategies you build will determine whether their silicon works.

What You'll Be Doing

• Lead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables
• Lead verification teams of 3-4 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios
• Develop verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve
• Integrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments
• Debug complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams
• Identify project risks early, propose mitigation strategies, and communicate status and blockers to Synopsys management and customer stakeholders
• Drive methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption

The Impact You Will Have

• Your verification plans and execution will directly determine whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems
• The engineers you mentor will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements
• Your early identification of design risks and verification gaps will prevent costly respins and post-silicon surprises for customers building chips in 5nm and below
• The methodology improvements you drive will reduce verification cycle time and improve coverage quality across dozens of SSG projects annually
• Your direct customer engagement will shape how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows
• The testbench architectures and VIP integration strategies you build will become reusable assets for future projects, compressing ramp time for new customer engagements
• Your technical leadership will help Synopsys win and retain customer relationships in high-performance computing, automotive, and aerospace markets where verification complexity is a competitive differentiator

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field with 5+ years of hands-on SoC, subsystem, or IP verification experience
• Deep technical expertise in UVM testbench development, coverage analysis, verification planning, and complex multi-domain debug
• Proven experience leading verification teams through full project cycles, including resource planning, task assignment, and delivery against customer schedules
• Strong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or DDR, and how they interact in real SoC architectures
• Hands-on proficiency with Synopsys VCS, Verdi or equivalent waveform analysis tools, and integration of third-party VIP into verification environments
• Experience with ARM-based technologies including Coresight debug infrastructure, processor architecture, or AMBA protocols is a strong plus
• Solid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development process

Who You Are

• You can walk into a customer meeting, hear a high-level SoC architecture description, and walk out with a verification plan that identifies the three highest-risk areas before anyone else in the room sees them
• When a regression fails at 3am and your team is stuck, you can look at the waveform, the coverage report, and the testbench code and know within 15 minutes whether it is a real bug or a testbench issue
• You give feedback that makes engineers better, not just feedback that makes you feel heard, and your team knows the difference
• You do not let a project drift. If a customer requirement is vague or a timeline is unrealistic, you say so early and propose a path forward that actually works
• You can explain a complex protocol violation to a customer architect, a verification coverage gap to your manager, and a UVM sequence bug to a junior engineer, and all three conversations will be clear and useful
• You stay current on verification methodology and tooling not because it is required but because you care about doing this work well, and you bring that knowledge back to your team

The Team You'll Be Part Of

You will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers across automotive, high-performance computing, aerospace, and defense. SSG works on everything from individual IP blocks to full turnkey SoCs, partnering with customers ranging from startups to industry leaders and government agencies. Your verification work will span subsystems and full chips, and you will collaborate closely with Synopsys architecture, design, EDA application engineering, and sales teams to deploy tool and IP solutions that solve real customer problems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.