RTL Engineer

Anthriq · Health Care · Web Design · SystemVerilog · 6 days ago
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Salary
≈ $29k – $61k per year (Estimated)
Location
In office (Bengaluru)
Experience
10+ years exp

First seen by Alion on Oct 23, 2026.

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Anthriq

Anthriq builds research-grade EEG, EMG, and EXG multimodal biosignal hardware and software infrastructure with supporting C++ and Python SDKs. The biosignal infrastructure platform for researchers, developers, and product teams.
anthriq.com · HQ: Bengaluru, India · Neurotech & Neuromodulation · Web Design · Health Care · 11-50 employees · Est. 2020
Tech stack of Anthriq
Backed by Gruhas

Responsibilities:

  • Translate the architecture specification into synthesizable SystemVerilog.
  • Own the RTL coding standards, linting rules, and design methodology.
  • Lead a team of 5-7 RTL engineers through the full design cycle.
  • Own the synthesis flow (Design Compiler or Genus) and drive timing closure.
  • Define and maintain SDC timing constraints.
  • Review all RTL code submissions for correctness, synthesizability, and style.
  • Coordinate with the outsource partner on GDSII handover (netlist, constraints, and floorplan guidance).
  • Work closely with the verification team to resolve bugs and achieve coverage closure.

Skills

Design Compiler, Genus, RTL, SystemVerilog, synthesis

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