Principal Compilers Engineer

We're looking for a Principal Compiler Engineer to own the system software stack that sits between Anthriq Silicon and the applications running on it, compiler infrastructure, low-level firmware, and real-time signal compute pipelines with sub-millisecond latency requirements. The ideal candidate has shipped production LLVM compiler pipelines at a semiconductor company, has hands-on embedded bring-up experience, and brings formal verification rigour to safety-critical real-time systems.

Responsibilities:

• Own custom LLVM backend passes, instruction selection (SelectionDAG / GlobalISel), MIR-level optimisations, and register allocator improvements for real-time execution paths.
• Build compiler fuzzing infrastructure and formal verification frameworks (Alive2 / SMT), with zero miscompilations in safety-critical pipelines.
• Implement device drivers and protocol stacks (USB, SPI, I2C, UART, PCIe, CAN) for real-time biosignal acquisition.
• Work with Linux kernel subsystems, RT-PREEMPT, SCHED_FIFO, and kernel modules for deterministic biosignal scheduling.
• Profile and optimise across CPU / GPU architectures using perf, gdb, Nsight, rocprof, valgrind, and eBPF.
• Author SRDs and SDDs; lead design reviews and mentor engineers across C++, LLVM, and embedded systems.
• Collaborate with hardware teams on silicon bring-up and BSP development ahead of tape-out.

Requirements:

• 12+ years in system-level C++ spanning GPU compiler engineering, embedded firmware, and kernel-adjacent work.
• Deep LLVM expertise: SelectionDAG, GlobalISel, MIR, register allocator, TableGen, custom pass development.
• Embedded Linux / RTOS (FreeRTOS, Zephyr) with hard real-time constraints; firmware bring-up across SPI / I2C / USB / PCIe / eMMC.
• GPU programming: CUDA / HIP; GPU execution model expertise (warp scheduling, register files, occupancy).
• Compiler correctness: fuzzing harnesses, formal verification (Alive2 SMT/SAT), differential testing.
• Advanced debugging: gdb, Lauterbach JTAG, logic/protocol analysers, AddressSanitizer.

Good to have:

• FPGA design (Verilog / VHDL) and assembly-level programming (PTX, GCN, SASS, x86 8051).
• DSP fundamentals or biosignal pipeline experience (EEG, EMG).

Skills

C++, LLVM, Linux, RTOS, compiler, embedded, firmware, kernel