Verification Engineer
Confirmed on the employer's own hiring board on Nov 2, 2026. First seen by Alion on Aug 27, 2026. AMD scores B on the Alion truth index.
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THE ROLE:
The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.
THE PERSON:
You are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.
KEY RESPONSIBILITIES:
- Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
- Interact with architects and design engineers to create a comprehensive verification test plan
- Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
- Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Debug tests with design engineers to deliver functionally correct design blocks
- Identify and write coverage measures for stimulus quality improvements
- Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
PREFERRED EXPERIENCE:
- Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
- Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
- Strong understanding of different phases of ASIC and/or full custom chip development is required.
- Experience in block level NOC (Net work on Chip) verification is a plus.
- Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
- Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.
THE PERSON:
You are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.
KEY RESPONSIBILITIES:
- Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
- Interact with architects and design engineers to create a comprehensive verification test plan
- Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
- Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Debug tests with design engineers to deliver functionally correct design blocks
- Identify and write coverage measures for stimulus quality improvements
- Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
PREFERRED EXPERIENCE:
- Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
- Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
- Strong understanding of different phases of ASIC and/or full custom chip development is required.
- Experience in block level NOC (Net work on Chip) verification is a plus.
- Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
- Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.