Senior RTL Design Engineer

We need a strong RTL expert who can join our silicon program to tape out. You will be the technical bridge between our architecture and our design partner, owning every step from RTL freeze to GDSII handoff, working with our partners. You write RTL, review RTL, run synthesis, and own the result. The architect defines what gets built. You own how it gets built.

Responsibilities:

• Translate the architecture specification into synthesizable SystemVerilog.
• Own the RTL coding standards, linting rules, and design methodology.
• Own the synthesis flow (Design Compiler or Genus) and drive timing closure.
• Define and maintain SDC timing constraints.
• Review all RTL code submissions for correctness, synthesizability, and style.
• Coordinate with the outsource partner on GDSII handover (netlist, constraints, floorplan guidance).
• Work closely with the verification team to resolve bugs and achieve coverage closure.

Requirements:

• 4+· years of RTL design experience in SystemVerilog.
• At least 1 tapeout through to GDSII (not just RTL — you've seen the full flow)·
• Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or Tempus).
• Processor, DSP, or datapath-heavy design experience.
• Familiarity with advanced process nodes (2·8nm class or below).
• Strong code review skills; you can spot timing hazards, FSM issues, and non-synthesizable patterns in review.

Good to have:

• VLIW or vector processor design experience.
• Experience with deterministic/real-time architectures (no caches, fixed latencies).
• Formal verification awareness (writing SVA, working with formal tools).
• SOC or FPGA prototyping experience (Vivado).

Soft Skills:

• Strong systems thinking with the ability to navigate large, complex FPGA architectures.
• Exceptional problem-solving under tight timing and resource constraints.
• Cross-functional collaboration with hardware, embedded software, DSP, and systems teams.
• Excellent communicator who documents clearly, presents confidently, and leads by example.
• Ability to make and defend architectural decisions under ambiguity and project pressure.

Skills

ASIC, RTL, SOC