CPU Implementation Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on block and full-chip EM/IR and electrical verification. Work on power grid and methodologies and implementation. Script using Perl/ Python to automate tasks and improve debug efficiency. Work with implementation/ CAD team during full design cycle to drive analysis fixes/signoff closure for takeout. Analysis and comparison of various tool methodologies to determine the best suited for Power grid construction. Work with the SOC team to meet IP analysis technical and delivery requirements. Work on complex C/C++ code base to do design optimization for power-grid convergence. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.

Experience and/or education must include:

Working on algorithmically complex tasks related to chip design using C or C++ programming

Programming in Perl, Python, or TCL scripting languages

Using Industry standard CAD/EDA tools like Cadence Virtuoso or Synopsys ICC/ICC2 design compiler to perform chip design implementation tasks

Performing EMIR and power grid analysis for industry designs with standard tools such as Cadence Voltus or Apache Redhawk

Reading and understanding Verilog RTL design descriptions

Implementing and operating Static timing analysis tools (i.e. Cadence Tempus or Synopsys Primetime)

Using circuit analysis tools such as HSPICE

Preferred Qualifications

N/A