CPU Implementation Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for central processing unit (CPU) development. Perform top-level physical design, integration, and physical verification of Apple CPUs. Responsible for full chip floorplan, area optimizations, block partitioning and pin placements using industry standard tools, including Encounter, ICC, and ICC2. Own chip level place and route (PnR), final CPU layout database construction and verification. Develop and validate Power Grid, including route-ability analysis. Drive custom layout integration, block and full-chip level EM/IR, bump/RDL design, electrical verification/analysis and formal verification. Work with the implementation and Computer Aided Design (CAD) teams during the entire chip design cycle to drive sign-off closure for tape-out. Work with System-on-Chip (SOC) team to meet IP technical and delivery requirements. Participate in establishing CAD and physical design methodologies to improve area and efficiency. Participate in flow development for chip integration and analysis using scripting languages TCL and Python. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 - $277,600/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 3 years of experience in the job offered or related occupation.

3 years of experience with each of the following skills is required:

Experience in full chip place and route, top metal layers routing utilizing the industry standard tools like Synopsys ICC or ICC2.

Utilizing TCL or Python for automation of PnR tasks, including chip layout analysis and PDV issues like DRC or LVS.

Experience in Bump or RDL design and top-level integration as part of top-level deliverables.

Experience in electrical issues involving Bump or RDL design for power delivery and chip functionality.

Utilizing Calibre for all layout verification like LVS, DRC, or Antenna, including experience in layout quality and fixes.

Utilizing device physics including device and transistor knowledge to understand design bottle necks

Experience in methodology developments and technology scaling impacts on design

Experience in planning, placement and knowledge of block level and SoC floor-plan.

Preferred Qualifications

N/A