Physical Design Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with logic design team to understand partition architecture and drive physical aspects early in design cycle; Complete netlist to GDS2 implementation for partition(s) meet schedule and design goals; Be responsible for timing, physical & electrical verification, driving the signoff closure for the partitions; Resolve design and flow issues related to physical design, identifying potential solutions and driving execution; Be a focal point for place and route, driving the work among place and route engineers, setting goals and milestones, planning short and long-term work, understanding dependencies between different domains like top, STA, block place and route; Work with physical design team, driving methodologies and "best known methods" to streamline physical design work, coming up with guidelines and checklists, driving execution, and tracking progress; Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors; Drive frontend and backend implementation from RTL to gds2, including synthesis, FV, floor planning, net listing, timing constraints, timing and power convergence, and ECO implementation; Be responsible for hands-on physical implementation and timing closure of core platforms and SoC's; Streamline the timing signoff criterions, timing analysis methodologies and flows and developing/enhancing ECO generation scripts for timing closure; Responsible for floor planning, physical synthesis, and physical design closure of large complex designs at 1GHz+ clock cycles; Drive physical design and timing convergence of high-frequency low-power at block level, cluster level, and/or full chip level. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or related field and 2 years of experience in the job offered or a related occupation.

Experience and/or education must include:

Utilizing PNR tools like ICC, ICC2, or Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs.

Utilizing timing analysis tools like Synopsys PrimeTime to be used for timing analysis, and timing ECO generation for timing closure of partitions on SoCs.

Utilizing TCL, Perl, or Python as well as Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure.

Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs.

Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs.

Understanding results from EMIR analysis tools like Voltus or Redhawk and generating fixes to address violations or improve QoR.

Understanding results from Physical verification tools like calibre and generating fixes to address violations.

Understanding results from LEC and Low Power verification tools like conformal, formality, VCLP and CLP, and make fixes to address the violations.

Preferred Qualifications

N/A