DFT Lead Engineer

Job Title :

Senior DFT Engineer

About the Role :

We are seeking a seasoned DFT professional to lead architecture, scan insertion, and compression efforts at both core and SoC levels. The role involves endtoend ATPG pattern generation, coverage analysis, and verification through timing and nontiming simulations, as well as implementation of MemoryBIST solutions. A solid grasp of SSN architecture, clock architecture, and OCC is essential.

Key Responsibilities :

- Design and implement DFT architecture, scan insertion, and compression strategies for core and SoC blocks.

- Generate ATPG patterns, perform coverage analysis, and ensure testability goals are met.

- Conduct timing and nontiming simulations to validate DFT implementations.

- Develop and integrate MemoryBIST schemes across target designs.

- Apply knowledge of SSN architecture, clock architecture, and OCC to optimize test structures.

- Collaborate with design, verification, and physical teams to resolve DFTrelated issues.

- Document DFT methodology, guidelines, and best practices for reuse across projects.

Required Experience :

- 8 to 13 years of overall professional experience in semiconductor design.

- 8 to 10+ years focused on DFT architecture, scan insertion, and compression at core and SoC levels.

- Proven experience with ATPG pattern generation and coverage analysis.

- Handson experience with timing and nontiming simulation environments.

- Experience implementing MemoryBIST solutions.

- Strong understanding of SSN architecture, clock architecture, and OCC concepts.

Preferred Skills :

- Familiarity with industrystandard DFT tools (e.g., Synopsys DFT, Mentor Tessent).

- Knowledge of lowpower design techniques and their impact on testability.

- Experience working in crossfunctional ASIC or SoC development teams.

Qualifications :

- Bachelors degree in Electrical Engineering, Computer Engineering, or a related field.

- Demonstrated ability to lead DFT initiatives and mentor junior engineers.

Recruiter Summary :

- 813 years total experience, with 810+ years in DFT architecture, scan insertion, and compression.

- Expertise in ATPG pattern generation, coverage analysis, and both timing and nontiming simulations.

- Proven track record delivering MemoryBIST implementations.

- Deep knowledge of SSN, clock, and OCC architectures.

- Strong collaborative skills across design, verification, and physical teams.

Skills

DFT, SoC, ATPG, MBIST