ASIC Design Engineer (Video Silicon IP)- Multimedia Lab
Confirmed on the employer's own hiring board on Nov 5, 2026. First seen by Alion on Jun 16, 2026. ByteDance scores A on the Alion truth index.
岗位职责 / Responsibilities
Team Introduction
The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities：
- As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
- Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
- Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
- Collaborate with algorithm teams to translate codec standard specifications and proprietary codec improvements into implementable hardware architectures.
- Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
- Drive functional correctness in partnership with the verification team using directed and constrained-random UVM test benches; debug and close RTL coverage metrics.
- Understand synthesis, timing analysis, and CDC/RDC checks; work with physical design on floor plan and timing closure guidance.
任职要求 / Requirements
Minimum Qualifications
- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 2 years of ASIC front-end design experience as a primary RTL owner.
- Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
- Familiarity with UVM/DPI/C++.
- Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
- Scripting proficiency in Python for EDA flow automation.
Preferred Qualifications:
- Experience with Video Codec (H.265/HEVC, H.266/VVC, AV1, VP9, or H.264/AVC) is a big plus.
- Experience with relevant ISP or machine learning based image/video compression.
- Experience with FPGA prototyping for pre-silicon codec validation.
- Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.