Principal Design Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Feb 24, 2025. Cadence Design Systems scores B on the Alion truth index.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title:Principal Design Engineer (Memory)
Location:Cork
Reports to:Design Engineering Director
Job Overview:
The Cadence Silicon Solutions Group (SSG) developleading edgeIntellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customersto tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume.
This is an opportunity to join a development team designing state-of-the-artDDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry.
The Principal Design Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, USand India.
JobResponsibilities:
Architect solutions for the latest DDR controller features and customer requirements.
Design RTL in a highly configurable and automated environment.
Work in small project teams.
Work across disciplines with Design Verification, Support, Delivery, Application Engineers, PHY design team, etc.
Utilize Cadence’s Design Automation flow and IP development tools.
Develop high speed circuits and low power features.
Improve quality and efficiency and help refine developmentprocess for greater productivity of the team through automation and improved methods.
Participate in an engineering team to advance our product.
Job Qualifications:
Degree in Electrical/ElectronicEngineering, Microelectronics, or a related discipline.
10+ years’ experience in microelectronics/EDA industry.
Experience of Verilog RTL Design essential.
Experience of Metric Driven Verification (MDV) essential.
Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
Experience of SoC Architecture and Development essential.
Experience of Technical Team leadership essential.
Excellent oral and written English essential.
Self-motivated with excellent planning, interpersonal, and communication skills.
Additional Skills/Preferences:
Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred.
Experience of SystemVerilogfor design preferred.
Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.