STA Application Engineer
Confirmed on the employer's own hiring board on Nov 8, 2026. First seen by Alion on Nov 6, 2026. Cadence Design Systems scores B on the Alion truth index.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies.
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows.
Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies.
Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.
Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts.
Execute and lead Tempus timing signoff campaigns at existing and new customers.
Automation of flows using scripting languages (Perl, Tcl, python).
Deliver technical trainings and seminars within Cadence and customer sites.
The annual salary range for California is $106,400 to $197,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.