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Location
In office (Beijing)
Seniority
Middle · 3+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 25, 2026. First seen by Alion on Dec 17, 2025. Cadence Design Systems scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

1.To provide key technical support in digital IC design implementation.

2.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power designs.

3.Have real design experience including logic equivalence checking, logic synthesis,

4.Have rich experience for RTL debug, RTL timing and power analysis.

5: Rich experience for Synthesis flow, and be familiar with backend implementation

Position Requirements:

1.Master/Bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.

2. Eager to learn new technologies, and willing to promote new technologies to customers

3.Requires working knowledge of one or more programming languages, and effective communication and soft skills.

4.Ability to debug all kinds of logic equivalent checking issues with formal tools(LEC, etc).

5.Ability to understand the low power design with UPF, IEEE1801, CPF,etc.

6.Have knowledge or experience in debugging the low power design issue with static check tools(ie. CLP ,etc).

7.Have experience in STA flow.

8.Have knowledge or experience in RTL coding is Plus.

We’re doing work that matters. Help us solve what others can’t.

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