Principal Product Validation Engineer

Cadence Design Systems • C++ • SystemVerilog • Verilog • VHDL • 3 years ago
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≈ $27k – $73k per year (Estimated)
Location
In office (Noida)
Seniority
Principal
Employment
Full-Time
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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Hardware • Simulation & Digital Twin • EDA • Semiconductors • Software • 5000+ employees • Est. 1988

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
  • Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
  • Experience in process automation with scripting.
  • Experience with SystemVerilog, C++, UVM.
  • Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
  • Experience designing and implementing complex functional verification environments is required.
  • Knowledge of protocols like PCIe, USB3/4, DP an added advantage.

We’re doing work that matters. Help us solve what others can’t.

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