743,678open jobs
45,086companies
108,908added this week
Browse all
Salary
≈ $85k – $170k per year (Estimated)
Location
In office (Austin)
Seniority
Middle · 2+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Sep 25, 2026. First seen by Alion on Sep 24, 2026. CesiumAstro scores B on the Alion truth index.

Overview
Company
Impact
Profile match
CesiumAstro is an American company founded in Austin in 2017 that builds active phased array communications payloads for satellites, aircraft and defence platforms. Its systems are software-defined and electronically steered, which lets a moving platform track several links at once without mechanical antennas, and the company manufactures them in house rather than integrating third-party subsystems. It sells mainly to defence customers and satellite operators, has raised venture funding from investors including Airbus Ventures and Lightspeed, and operates facilities in Austin, Colorado and the United Kingdom.

We are looking to add an FPGA Engineer II to our team. If you enjoy working in a startup environment, and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.

In this position, you will contribute to the development of FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also desirable.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

  • Bachelor of Science (BS) or Master of Science (MS) degree in Electrical Engineering or Computer Engineering from an accredited university or institution.
  • Minimum of 2 years of industry experience in the design, analysis, and implementation of FPGA systems at the HDL level.
  • Expertise in FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim, etc.).
  • Hands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.
  • Excellent written and verbal communication skills.

PREFERRED EXPERIENCE

  • Aerospace design and qualification.
  • Worst-case analysis, failure method and criticality analyses, and reliability analysis.
  • Experience with board-level hardware design.
  • Familiarity with communications systems, such as digital signal processing.
Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
743,678 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Austin
$160k – $275k per year • Hybrid • Full-Time • 8+ years exp • Bachelor's Degree • Mountain View
Python
Perl
DevOps
Wi-Fi
Apply
ASIC/SOC CAD Engineer 2 years ago
$160k – $275k per year • Hybrid • Full-Time • 8+ years exp • Bachelor's Degree • Mountain View
Python
Perl
DevOps
Wi-Fi
Apply
$160k – $275k per year • Hybrid • Full-Time • 8+ years exp • Bachelor's Degree • Mountain View
Python
Verilog
SystemVerilog
Perl
DevOps
Wi-Fi
Chips/EDA
Synopsys PrimeTime
Apply
≈ $136k – $250k per year (Estimated) • In office • Full-Time • 7+ years exp • Mountain View
AI/ML
LLM
DevOps
Wi-Fi
Chips/EDA
Cadence Allegro
Cadence Sigrity
Ansys SIwave
Apply
$160k – $275k per year • Hybrid • Full-Time • 5+ years exp • Mountain View
AI/ML
LLM
DevOps
Wi-Fi
Management
Agile
Apply
$140k – $168k per year • In office • Full-Time • 6+ years exp • Bachelor's Degree • El Segundo
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
≈ $107k – $198k per year (Estimated) • In office • Full-Time • 6+ years exp • Bachelor's Degree • Austin
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
$133k – $161k per year • In office • Full-Time • 6+ years exp • Bachelor's Degree • Westminster
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
FPGA Engineer II 1 day ago
$113k – $136k per year • In office • Full-Time • 2+ years exp • Bachelor's Degree • Westminster
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
$193k – $236k per year • In office • Full-Time • Bachelor's Degree • El Segundo
Verilog
VHDL
Chips/EDA
Siemens ModelSim
HDL Coder
Management
Agile
Apply
$193k – $236k per year • In office • Full-Time • Bachelor's Degree • El Segundo
Verilog
VHDL
Chips/EDA
Siemens ModelSim
HDL Coder
Management
Agile
Apply
$184k – $225k per year • In office • Full-Time • Bachelor's Degree • Westminster
Verilog
VHDL
Chips/EDA
Siemens ModelSim
HDL Coder
Management
Agile
Apply
≈ $127k – $236k per year (Estimated) • In office • Full-Time • Bachelor's Degree • Austin
Verilog
VHDL
Chips/EDA
Siemens ModelSim
HDL Coder
Management
Agile
Apply
$140k – $168k per year • In office • Full-Time • 6+ years exp • Bachelor's Degree • El Segundo
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
≈ $107k – $198k per year (Estimated) • In office • Full-Time • 6+ years exp • Bachelor's Degree • Austin
Verilog
VHDL
Chips/EDA
Siemens ModelSim
Xilinx Vivado
HDL Coder
Apply
≈ $98k – $223k per year (Estimated) • In office • Austin
Apply
≈ $121k – $222k per year (Estimated) • In office • Austin
SystemVerilog
DevOps
HPC
Apply
≈ $127k – $245k per year (Estimated) • In office • Austin
DevOps
Wi-Fi
Apply
≈ $108k – $199k per year (Estimated) • In office • Austin
DevOps
Wi-Fi
Apply
≈ $100k – $226k per year (Estimated) • In office • Austin
SystemVerilog
DevOps
Wi-Fi
Apply
See all jobs
This is one of many
743,678 more open roles from verified company boards, updated every day.