Senior Engineer - STA

Key Responsibilities

Static Timing Analysis & Signoff

• Perform block-level and full-chip timing analysis and signoff.
• Drive timing closure across all functional and test modes.
• Analyze and fix setup, hold, recovery, removal, transition, capacitance, and pulse-width violations.
• Perform timing signoff across multiple process, voltage, and temperature corners.
• Execute MCMM (Multi-Corner Multi-Mode) timing analysis and closure.
• Validate timing across hierarchical and flat SoC designs.

Timing Closure

• Drive setup and hold optimization throughout implementation cycles.
• Work closely with Physical Design teams to achieve timing convergence.
• Perform timing ECO generation and validation.
• Analyze critical timing paths and propose optimization strategies.
• Resolve timing bottlenecks while maintaining area and power targets.
• Support late-stage tapeout closure activities.

Cadence Signoff Flow

Strong hands-on experience in:

• Cadence Tempus Timing Signoff
• Cadence Innovus Timing Analysis
• Cadence Voltus Integration
• Cadence Quantus Extraction
• Cadence Conformal ECO
• Cadence Genus Synthesis (preferred)

Signal Integrity & Noise Analysis

• Perform Crosstalk Analysis.
• Analyze and resolve SI-related timing issues.
• Validate noise, glitches, and signal integrity effects.
• Work closely with physical design teams on route optimization and shielding techniques.
• Ensure timing robustness under SI effects.

Low Power Verification

• Verify clock gating implementations.
• Analyze UPF/CPF constraints.
• Validate low-power modes and timing requirements.
• Support power-aware timing signoff methodology.

ECO Implementation & Verification

• Generate timing ECOs for setup and hold closure.
• Work with implementation teams to validate ECO impact.
• Perform incremental timing signoff after ECO implementation.
• Ensure clean final signoff before tapeout.

Cross-Functional Collaboration

• Collaborate with:
  • RTL Design Teams
  • Physical Design Teams
  • DFT Engineers
  • Verification Teams
  • Architecture Teams
  • Foundry Support Teams
• Participate in design reviews and closure meetings.
• Support project execution from RTL freeze to tapeout.

Mandatory Technical Skills

Cadence Tool Expertise

Strong hands-on experience in:

Timing & Signoff

• Cadence Tempus
• Cadence Innovus
• Cadence Quantus
• Cadence Voltus

ECO & Verification

• Cadence Conformal ECO
• Conformal LEC

Synthesis (Preferred)

• Cadence Genus

STA Expertise

Strong knowledge of:

Static Timing Analysis (STA)

MCMM Timing Closure

Full Chip Timing Signoff

Block Level Timing Signoff

Timing ECO Closure

Constraint Development (SDC)

Path-Based Analysis

Graph-Based Analysis

Clock Tree Analysis

Timing Exception Validation

Setup/Hold Closure

Recovery & Removal Checks

Clock Domain Analysis

CDC Timing Understanding

Timing Constraints Knowledge

Strong expertise in:

• SDC Creation and Validation
• Generated Clocks
• Virtual Clocks
• False Paths
• Multi-Cycle Paths
• Asynchronous Path Constraints
• Timing Derates
• OCV/AOCV/POCV
• Useful Skew Methodology

Signal Integrity & Variability Analysis

Experience in:

• Crosstalk Analysis
• Noise Analysis
• OCV Closure
• AOCV
• POCV
• LVF-Based Flows
• Variation-Aware Timing Signoff

Technology Node Experience

Mandatory experience in one or more:

• 28nm
• 16nm FinFET
• 12nm FinFET
• 7nm FinFET
• 5nm FinFET

Preferred:

• 3nm Technology Node
• Advanced FinFET Implementation
• Multi-billion Gate SoCs

4. DFT: Synopsys Tool: