Staff Digital Design Engineer (PHY)

Join Eliyan, a leading chiplet startup, as a Staff Digital Design Engineer. In this hands-on technical leadership role, you will lead the frontend design of our D2D PHY, the core technology behind our chiplet interconnect platform. You will work closely with architecture, analog, verification, and physical design teams, and your work will directly enable next-gen chiplet-based AI and HPC systems.

Missions

• Lead the frontend design of the D2D PHY, from microarchitecture definition through synthesis and physical design handoff.
• Collaborate with architecture, analog, verification, and physical design teams to ensure clean integration across the stack.
• Mentor and guide junior digital designers on frontend design and synthesis optimization, driving design reviews and technical decisions.

Profil recherché

- Expert SystemVerilog RTL design with strong synthesis optimization skills

- Experience with SDC constraints, UPF, STA methodology

- 8+ years digital frontend design with 4+ years in PHY or high-speed interfaces

- Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes

- Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)

- Advanced CDC design, link training protocols, elastic buffer architectures

- Deep expertise in D2D PHY, DDR PHY, or SerDes digital design

- 3+ successful tapeouts as design lead in advanced nodes (7nm or below)

- 12+ years with demonstrated technical leadership

- UCIe PHY design or certification experience

- SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience

- DDR4/DDR5/LPDDR PHY or DFI interface experience

- Advanced packaging knowledge: 2.5D, 3D, organic substrate

- Firmware development for PHY control or low-level driver implementation

- Publications or patents in PHY design

- Python/Perl/Tcl scripting for design automation