2,081,199open jobs
123,213companies
245,271added this week
Browse all
Location
In office
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 30, 2026. First seen by Alion on Sep 14, 2026.

Overview
Company
Impact
Profile match
Everspin is the global MRAM leader pioneering persistent memory innovation, quality, and reliability for mission‑critical applications since 2006.
Backed by Lux Capital

Analog Design Engineer

About Everspin

Headquartered in Chandler, Arizona, Everspin Technologies (Nasdaq: MRAM) is the worldwide leader in designing, manufacturing, and commercially shipping discrete and embedded Magnetoresistive RAM (MRAM) into markets and applications where data persistence and integrity, low latency, and security are paramount. With over 120 Million MRAM products deployed in data center, cloud storage, energy, industrial, automotive, and transportation markets, Everspin has built the strongest and fastest growing foundation of MRAM users in the world. For more information, visit www.everspin.com.

The Role

Reporting to the Sr. Director of Design and based in our Austin, Texas location, s/he will work on innovative memory products.

Specific responsibilities will include:

  • Work with analog team members for memory array design, defining array bias requirements, and developing the architecture
  • Hands-on work and ownership of multiple analog circuit building blocks, such as sense amplifiers, write and wordline drivers, charge pumps, bandgaps, op-amps, voltage regulators, IO drivers & receivers, oscillators, power supply detectors, and current distribution networks
  • Drive low power, low noise design techniques, and high precision bias techniques in presence of device mismatch and process variation
  • Work with product and test engineers for test plans and reviewing lab test results to drive bug fixes and yield improvements
  • Run analog design verification flows (e.g. spice, fast-spice, electromigration, IR drop, aging, etc.) to verify a design is ready for tape-out
  • Document design simulation and verification for formal design reviews
  • Support layout designers and drive final layout through post-layout and top-level simulations to validate top-level integration.

Qualifications & competencies

  • MS or higher degree in Electrical or Computer Engineering or Computer Science desired
  • Experience in analog circuit design with a proven track record of memory, bias circuits design in silicon
  • Deep understanding of transistor operation, device physics, and analog design techniques
  • Strong circuit analysis skills (e.g., AC/DC/Transient circuit analysis, small signal circuit techniques, feedback compensation, statistics, etc.)
  • Knowledge of memory interface protocols, such as SPI and DDR, and Cadence tools are preferred but not required.
  • Must have strong communication skills and be a team player
  • Unquestionable ethics - treats people with respect; keeps commitments; inspires the trust of others; works with integrity.
  • Commitment to our core values of Leadership, Innovation, Communication, Persistence, Enthusiasm, and Respect

Contact us:

https://www.everspin.com/careers-everspin

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
2,081,199 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Recommended for you based on this role

Industrial Engineering
Similar stack
Same company
In your city
$163k – $215k per year · In office · Full-Time · 8+ years exp · Bachelor's Degree · San Francisco
Apply
In office · Full-Time · 3+ years exp · Pune
AI/ML
Claude
ChatGPT
Perplexity
Analytics
A/B Testing
Management
Notion
Apply
≈ $55k – $100k per year (Estimated) · In office · 2+ years exp · High School Diploma · United States
Apply
$36k – $38k per year · In office · Full-Time · Richardson
Apply
Senior Cell Engineer 3 hours ago
$112k – $160k per year · In office · 5+ years exp · PhD · Hayward
Life Sciences
Design of Experiments
Energy
Electrochemical Impedance Spectroscopy
Apply
≈ $107k – $196k per year (Estimated) · In office · Full-Time · 5+ years exp · Bachelor's Degree · Chandler
Chips/EDA
Statistical Process Control
JMP
Life Sciences
Design of Experiments
Apply
SMTS (Product Eng) 7 months ago
≈ $103k – $223k per year (Estimated) · In office · Bachelor's Degree · Chandler
Python
Chips/EDA
JMP
Apply
See all jobs
This is one of many
2,081,199 more open roles from verified company boards, updated every day.