Hardware Engineer, TPU Interconnect and Packaging

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Hardware Engineer in the Interconnect and Packaging team, you will serve as a technical lead driving the architectural strategy, co-design methodologies, and technology roadmaps for TPU interconnects and optical packaging. You will bridge hardware architecture with foundry manufacturing capability, leading cross-functional teams across silicon photonics, high-density substrates, and system integration to deliver multi-terabit packaging capabilities.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define the architectural strategy and package technology selection for next-generation TPU systems, incorporating 2.5D/3D interposers, embedded bridges, and CPO modules.
• Drive electro-optical co-design across silicon photonics dies, laser sources, package substrates, and drive electronics to maximize interconnect bandwidth density and energy efficiency.
• Establish signal integrity, power delivery, thermal management, and mechanical robustness design rules across multi-chiplet heterogeneous assemblies.
• Partner with OSAT vendors, foundries, and optical component suppliers to co-develop custom substrate processes, sub-micron alignment flows, and optical coupling interfaces.
• Lead full-lifecycle technology qualification from pathfinding and architectural simulation through to mass production readiness.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with semiconductor packaging, integration, or interconnect design.
• Experience with interconnect modeling, 2.5D/3D interposer design rules, or chiplet package assembly.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience leading complex package development programs for high-performance computing (HPC) or AI accelerator platforms.
• Experience in silicon photonics integration, Co-Packaged Optics (CPO), 2.5D silicon interposers, and high-density substrate routing.
• Knowledge of wafer-level packaging (WLP), chiplet interconnect standards, dynamic thermal control, and high-density power delivery networks.
• Ability to deliver first-of-a-kind optical packaging or heterogeneous 3D integration solutions into production systems.