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Package Design/Technology/Layout Engineer

Google • Digital Media • Marketing Analytics & Attribution • Bachelor's Degree • 2 hours ago
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Salary
≈ $63k – $153k per year (Estimated)
Location
In office (Haifa)
Seniority
Junior · 1+ year exp

Confirmed on the employer's own hiring board on Oct 16, 2026. First seen by Alion on Oct 16, 2026. Google scores B on the Alion truth index.

Overview
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Profile match

Google

Google is an American technology company founded in 1998 by Larry Page and Sergey Brin and now the principal subsidiary of Alphabet, headquartered in Mountain View, California. It operates the world's dominant search engine and the advertising system built around it, along with YouTube, Android, Chrome, Gmail, Maps, Workspace and Google Cloud, reaching billions of users across nearly every internet-connected market. The company designs its own silicon in the Tensor Processing Unit line, develops the Gemini foundation models through Google DeepMind, and derives most of its revenue from advertising while cloud has become its fastest growing segment.
google.com • HQ: Mountain View, United States • Digital Media • Marketing Analytics & Attribution • Streaming & OTT Platforms • Consumer Internet Groups • Foundation Models • Operating Systems • Cloud Platforms (IaaS & PaaS) • Video & Photo Sharing • Advertising • Search Engines • 11-50 employees • Est. 1998
Tech stack of Google
Backed by Y Combinator, Lightspeed Venture Partners, Union Square Ventures

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Drive the physical layout of high-performance package substrates, from initial bump/ball map feasibility and pin-out optimization to final Gerber/GDS release.
  • Design and layout complex 2.5D/3D architectures, including flip-chip BGA (FCBGA), Silicon Interposers (CoWoS).
  • Partner with SoC designers and System board engineers to co-optimize die-to-package and package-to-board interconnects, and work intimately with Signal and Power Integrity teams to optimize trace routing, decoupling capacitor placement, and power plane geometries to meet electrical targets.
  • Interface with leading foundries and OSATs to evaluate new packaging technologies, establish Design Rule Checks (DRC), and influence future package technology roadmaps, and develop scripts and CAD methodologies to automate tedious layout tasks, improve design quality, and shorten cycle times.

Qualifications

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 1 year of experience with semiconductor package design and substrate layout.
  • Experience with industry-standard packaging EDA tools such as Cadence APD/APD+, Cadence Allegro, or Siemens/Mentor Xpedition.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Strong understanding of substrate manufacturing processes, materials, and design rules.
  • Proven track record of taping out high-pin-count, high-speed flip-chip packages.
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