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Salary
≈ $101k – $204k per year (Estimated)
Location
In office (Mountain View)
Seniority
Middle · 4+ years exp

Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Sep 4, 2026.

Overview
Company
Impact
Profile match
Google is an American technology company founded in 1998 by Larry Page and Sergey Brin and now the principal subsidiary of Alphabet, headquartered in Mountain View, California. It operates the world's dominant search engine and the advertising system built around it, along with YouTube, Android, Chrome, Gmail, Maps, Workspace and Google Cloud, reaching billions of users across nearly every internet-connected market. The company designs its own silicon in the Tensor Processing Unit line, develops the Gemini foundation models through Google DeepMind, and derives most of its revenue from advertising while cloud has become its fastest growing segment.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
  • Manage full-chip level physical implementation.
  • Define and implement innovative schemes to improve performance and power.
  • Work with cross-functional teams to deliver best quality of results.

Qualifications

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience in physical design.
  • Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
  • Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

  • Experience in top-level floorplanning and block integration.
  • Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
  • Experience with ASIC design flows and methodology of physical design.
  • Understanding of circuit design, device physics, and deep submicron technology.
  • Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
  • Effective skills with scripting languages such as Tcl, or Perl.
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