Salary
≈ $109k – $218k per year (Estimated)
Location
In office (Mountain View)
Seniority
Middle · 4+ years exp
Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Sep 25, 2026. Google scores B on the Alion truth index.
Overview
Company
Impact
Profile match
Google is an American technology company founded in 1998 by Larry Page and Sergey Brin and now the principal subsidiary of Alphabet, headquartered in Mountain View, California. It operates the world's dominant search engine and the advertising system built around it, along with YouTube, Android, Chrome, Gmail, Maps, Workspace and Google Cloud, reaching billions of users across nearly every internet-connected market. The company designs its own silicon in the Tensor Processing Unit line, develops the Gemini foundation models through Google DeepMind, and derives most of its revenue from advertising while cloud has become its fastest growing segment.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
- Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
- Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
- Debug test failures alongside design engineers to ensure functionally correct design blocks.
- Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
- Experience with interconnect protocols such as AXI, APB, and ACE.
- Experience building and maintaining verification test benches, test cases, and test environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience managing the full verification life cycle, from initial test planning through coverage closure.
- Expertise in advanced verification methodologies and techniques (including UVM, formal verification, and UPF-based power simulations) to ensure bug-free silicon in complex SoCs.
- Strong problem-solving and communication skills, with the ability to collaborate effectively in a team setting.
Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
859,529 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Free forever. No card. Under a minute.
Your match
How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.
Recommended for you based on this role
Hardware
Similar stack
Same company
Mountain View
Sr Analytics Developer Epic
26 days ago
$131k – $218k per year • In office • Full-Time • 6+ years exp • United States
SQL
Databases
Oracle
MS SQL
Analytics
Tableau
Power BI
SAP BusinessObjects
Apply
Electrical Controls Engineer
2 months ago
≈ $84k – $170k per year (Estimated) • In office • Full-Time • 3+ years exp • Bachelor's Degree • Green Bay
Python
MATLAB
Design
AutoCAD
Apply
Electrical Engineer - All Levels
2 months ago
≈ $64k – $128k per year (Estimated) • Hybrid • Full-Time • Bachelor's Degree • Madison
Design
AutoCAD
Apply
Electrical Engineer
2 months ago
≈ $102k – $188k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Baltimore
Apply
Field Applications Engineer
1 month ago
≈ $123k – $227k per year (Estimated) • In office • Full-Time • 7+ years exp • Bachelor's Degree • San Jose • Hillsboro
Verilog
VHDL
Apply
≈ $70k – $151k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Reading
Verilog
SystemVerilog
Chips/EDA
UVM
Apply
ASIC Digital Design, Sr Manager-18780
1 day ago
≈ $54k – $117k per year (Estimated) • In office • 15+ years exp • Hsinchu
Python
Verilog
SystemVerilog
Perl
Chips/EDA
UVM
Apply
≈ $60k – $143k per year (Estimated) • In office • 15+ years exp • Bachelor's Degree • Hsinchu
Python
Verilog
C++
SystemVerilog
Perl
TCL Scripting
DevOps
Unix
Chips/EDA
UVM
Formal Verification
Apply
≈ $128k – $230k per year (Estimated) • In office • Mississauga
SystemVerilog
Chips/EDA
UVM
Apply
≈ $70k – $141k per year (Estimated) • In office • Maia
SystemVerilog
Chips/EDA
UVM
Apply
Principal Engineer, Silicon Engineering
2 days ago
≈ $161k – $312k per year (Estimated) • In office • 10+ years exp • Bachelor's Degree • Mountain View
AI/ML
AI Agents
Apply
≈ $153k – $285k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Sunnyvale
C++
AI/ML
Vertex AI
TPU
Edge AI
DevOps
GCP
Apply
≈ $129k – $238k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Sunnyvale
Python
AI/ML
Vertex AI
TPU
Edge AI
DevOps
GCP
Apply
≈ $128k – $237k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Mountain View
Verilog
SystemVerilog
Perl
Apply
TPU Design Engineer, Silicon
2 days ago
≈ $105k – $211k per year (Estimated) • In office • 4+ years exp • Bachelor's Degree • Mountain View
Verilog
SystemVerilog
AI/ML
Machine Learning
Apply
Senior Design Engineer, RTL
1 day ago
≈ $131k – $241k per year (Estimated) • In office • 8+ years exp • Bachelor's Degree • Mountain View
Verilog
VHDL
Chips/EDA
Formal Verification
Apply
RTL Design Engineer, Silicon
1 day ago
≈ $101k – $203k per year (Estimated) • In office • 4+ years exp • Bachelor's Degree • Mountain View
Python
Verilog
VHDL
Perl
Apply
People Operations Associate
1 day ago
≈ $71k – $141k per year (Estimated) • In office • Full-Time • 4+ years exp • Mountain View
DevOps
Wi-Fi
Apply
Senior Mechanical Engineer
1 day ago
$180k – $205k per year • Equity • In office • 7+ years exp • Bachelor's Degree • Mountain View
Design
SolidWorks
AutoCAD
Apply
≈ $113k – $223k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Mountain View
Apply
This is one of many
859,529 more open roles from verified company boards, updated every day.

