Salary
≈ $109k – $218k per year (Estimated)
Location
In office (Mountain View)
Seniority
Middle · 4+ years exp
Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Sep 25, 2026.
Overview
Company
Impact
Profile match
Google is an American technology company founded in 1998 by Larry Page and Sergey Brin and now the principal subsidiary of Alphabet, headquartered in Mountain View, California. It operates the world's dominant search engine and the advertising system built around it, along with YouTube, Android, Chrome, Gmail, Maps, Workspace and Google Cloud, reaching billions of users across nearly every internet-connected market. The company designs its own silicon in the Tensor Processing Unit line, develops the Gemini foundation models through Google DeepMind, and derives most of its revenue from advertising while cloud has become its fastest growing segment.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
- Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
- Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
- Debug test failures alongside design engineers to ensure functionally correct design blocks.
- Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
- Experience with interconnect protocols such as AXI, APB, and ACE.
- Experience building and maintaining verification test benches, test cases, and test environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience managing the full verification life cycle, from initial test planning through coverage closure.
- Expertise in advanced verification methodologies and techniques (including UVM, formal verification, and UPF-based power simulations) to ensure bug-free silicon in complex SoCs.
- Strong problem-solving and communication skills, with the ability to collaborate effectively in a team setting.
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