RTL Design Engineer, Silicon

Google • Operating Systems • Streaming & OTT Platforms • Bachelor's Degree • Python • Verilog • VHDL • Perl • 2 hours ago
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Salary
≈ $101k – $203k per year (Estimated)
Location
In office (Mountain View)
Seniority
Middle · 4+ years exp

Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Aug 13, 2026.

Overview
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Google

Google is an American technology company founded in 1998 by Larry Page and Sergey Brin and now the principal subsidiary of Alphabet, headquartered in Mountain View, California. It operates the world's dominant search engine and the advertising system built around it, along with YouTube, Android, Chrome, Gmail, Maps, Workspace and Google Cloud, reaching billions of users across nearly every internet-connected market. The company designs its own silicon in the Tensor Processing Unit line, develops the Gemini foundation models through Google DeepMind, and derives most of its revenue from advertising while cloud has become its fastest growing segment.
google.com • HQ: Mountain View, United States • Streaming & OTT Platforms • Consumer Internet Groups • Foundation Models • Operating Systems • Cloud Platforms (IaaS & PaaS) • Video & Photo Sharing • Advertising • Search Engines • 11-50 employees • Est. 1998
Tech stack of Google

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Define microarchitecture for a subsystem.
  • Integrate internal and/or external IP.
  • Define microarchitecture of a small to medium size IP.
  • Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Qualifications

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with IP development or integration.
  • Experience in ASIC development with Verilog or VHDL.
  • Experience with a scripting language like Perl or Python.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
  • Knowledge of high-performance and energy efficient design techniques.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of ASIC Verification or DFT.
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