Physical Designer Engineer, Google Cloud

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Qualifications

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience with System on a Chip (SoC) cycles.
• Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master’s degree in Electrical Engineering, or a related field.

• Experience coding with System Verilog and scripting with Transaction Control Language (TCL).

• Experience with Very Large Scale Integration (VLSI) design in SoC.
• Experience with multiple-cycles of SoC in ASIC design.
• Experience with layout verification and design rules.