Silicon Test Engineer, SOC, ASIC

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Design, implement, and manage Integrated Circuit (IC) product bring-up, verification, and characterization programs for NPI, including ATE test programs, load boards, and probe cards using ATE platforms such as UFLEX or 93K.
• Drive test development, validation, and characterization for high-speed interfaces including DDR memory and High-Speed I/O (HSIO) IPs, ensuring production screen enabement and low Defective Parts Per Million (DPPM).
• Collaborate with vendors and internal teams to engineer high-volume ATE manufacturing solutions tailored for advanced packaging.
• Execute product and DPPM correlation between ATE and system-level environments for new products, and enhance test coverage and resolve the failure modes via rigorous troubleshooting on ATE and SLT systems.
• Direct production sustaining activities, including program upgrades, yield optimization, test time reduction, lot disposition, and RMA analysis.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, or equivalent practical experience.
• 8 years of experience in Semiconductor Domain.
• Experience in ATE test program development, hardware architecture, and post-silicon bring-up for complex Digital/Mixed-Signal SoCs.
• Experience in ASIC/SoC test development, bring-up, or debug.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with ATE platforms (Teradyne UltraFlex SOC and Advantest 93K) and knowledge of high-speed interfaces (DDR, PCIe, SERDES).
• Proven track record in semiconductor processing, VLSI product/test engineering, with SLT expertise using the Advantest platform.
• Proficiency in DFT methodologies, including memory BIST, JTAG, Scan/ATPG, and testing for PVT and temperature sensors.
• Expertise in Test Time Reduction (TTR) strategies, Gage R&R, DPPM reduction, and statistical yield analysis.