Silicon Validation Engineer AI/ML, Google Cloud

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Study the instruction set and architecture of the Machine Learning (ML) IPs and drive discussions on the delta features from the previous generation.
• Develop functional or performance models for the ML IPs. Integrate the functional models with the Cloud TPU SoC model and deliver the single source of truth architectural reference.
• Work with pre-silicon verification and post-silicon validation teams to deploy the models into their validation flows.
• Work with compiler and software teams to enable them to left-shift their development activity.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience in developing simulation models for hardware IPs, or a PhD.
• Experience in developing software systems in modern C++.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in applying computer architecture principles to solve open-ended problems.
• Experience in hardware and software co-design.
• Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog.
• Knowledge of processor design or accelerator designs and mapping ML models to hardware architectures.