SoC DFT Engineer, Cloud

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Engineer you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
• Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
• Develop diagnostic databases, software and hardware for logic and memory fail debug.
• Design and implement system level test strategy.
• Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
• Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
• Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).