Staff Hardware Engineer, TPU Interconnect and Packaging

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Staff Hardware Engineer in the Interconnect and Packaging team, you will serve as a technical lead driving technology roadmaps for Tensor Processing Unit (TPU) interconnects and optical packaging. You will bridge hardware architecture with foundry manufacturing capability, leading cross-functional teams to deliver multi-terabit packaging capabilities.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define the architectural strategy and package technology selection for next-generation TPU systems, incorporating 2.5D/3D interposers, embedded bridges, and co-packaged optics (CPO) modules.
• Drive electro-optical co-design across silicon photonics dies, laser sources, package substrates, and drive electronics to maximize interconnect bandwidth density and energy efficiency.
• Establish signal integrity, power delivery, thermal management, and mechanical design rules across multi-chiplet heterogeneous assemblies.
• Partner with outsourced semiconductor assembly and test (OSAT) vendors, foundries, and optical component suppliers to co-develop custom substrate processes, sub-micron alignment flows, and optical coupling interfaces.
• Lead full-lifecycle technology qualification from pathfinding and architectural simulation through to mass production readiness, while mentoring engineers, fostering technical excellence, and driving engineering best practices across the organization.

Qualifications

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Materials Science, Optical Engineering, Microelectronics, a related technical field, or equivalent practical experience.
• 10 years of experience in semiconductor packaging, integration, or interconnect design.
• Experience with interconnect modeling, 2.5D/3D interposer design rules, or chiplet package assembly.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Optical Science, Materials Science, or a related technical discipline.
• Technical expertise in silicon photonics integration, Co-Packaged Optics (CPO), 2.5D silicon interposers, and high-density substrate routing.
• Deep knowledge of wafer-level packaging (WLP), chiplet interconnect standards, dynamic thermal control, and high-density power delivery networks.
• Demonstrated success in delivering first-of-a-kind optical packaging or heterogeneous 3D integration solutions into production systems.
• Track record of leading complex package development programs for high-performance computing (HPC) or AI accelerator platforms.