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Salary
$214k – $278k per year
Location
Remote (San Francisco, United States)
Seniority
Principal · 12+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Sep 30, 2026. Hayden AI scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Hayden AI is an American artificial intelligence technology company specializing in smart city solutions and automated traffic enforcement. Founded in 2019, the company utilizes mobile computer vision and edge processing systems—often mounted on public transit buses—to detect parking and traffic violations in real time. By automating enforcement in bus lanes and stop zones, it helps municipalities improve urban transit efficiency, enhance pedestrian safety, and reduce city traffic congestion.

About Us

At Hayden AI, we are on a mission to harness the power of computer vision to transform the way transit systems and other government agencies address real-world challenges.

From bus lane and bus stop enforcement to transportation optimization technologies and beyond, our innovative mobile perception system empowers our clients to accelerate transit, enhance street safety, and drive toward a sustainable future.

What the job involves

The Principal Technical Program Manager will lead the development and execution of a portfolio of hardware programs. This role will collaborate with leaders across Hayden in highly ambiguous conditions to drive strategy into roadmaps and plans that deliver critical work on time and at high quality. They will set the standard for program excellence across the entire product lifecycle and drive systemic improvements across the company.

Responsibilities:

  • Strategic Execution: Drive end-to-end delivery of enterprise engineering programs, bridging executive business goals and technical execution.

  • Edge AI & On-Vehicle Systems: Partner with Perception and Platform engineering to ensure hardware programs account for the full edge inference stack - thermal envelope, compute constraints, sensor integration, and field serviceability - so that AI system requirements drive hardware decisions from day one.

  • Advanced R&D & Technology Incubation: Partner with engineering leadership to drive early-stage R&D efforts, including proof-of-concepts (PoCs) and the rigorous evaluation of next-generation components, shaping the N+1 and N+2 product roadmaps.

  • Phase Gate & Milestone Governance: Define, implement, and rigorously enforce phase gate reviews and program milestones across the hardware lifecycle. Ensure cross-functional readiness, quality standards, and executive alignment before advancing products to subsequent development phases.

  • NPI Lifecycle & Manufacturing: Drive the end-to-end New Product Introduction (NPI) process (EVT, DVT, PVT) and oversee vendor delivery to ensure a seamless transition from prototype to Mass Production (MP).

  • Requirements & Scope Definition: Partner with Engineering and Growth to shape what gets built at the hardware level - translating field feedback, customer deployment constraints, and regulatory requirements into clear hardware requirements before design begins, and holding the line on scope when program objectives drift.

Required Qualifications:

  • B.S., M.S., or Ph.D. in an engineering discipline

  • 12+ years in Hardware TPM or Engineering Program Management

  • Led 5+ multi-disciplinary hardware products from 0-to-1 through production

  • Deep knowledge of NPI lifecycle (EVT, DVT, PVT, MP), phase gate governance, and CM/supplier management

  • Experience with hardware reliability, regulatory compliance (FCC, CE), and supply chain risk

  • Strong technical foundation in embedded systems, hardware/software integration, or computer vision systems

Preferred Qualifications

  • Experience with on-vehicle, edge-deployed, or ruggedized hardware

  • Background in autonomous systems, robotics, or AI/ML hardware programs

  • Experience delivering technology to government or municipal clients

  • Familiarity with DFX methodologies (DFA, DFI, DFS)

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