Design Lead

HCLTech • IT Consulting & Digital Transformation • IT Outsourcing & Dedicated Teams • Verilog • 2 days ago
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Salary
≈ $21k – $49k per year (Estimated)
Location
In office (Hanoi)
Seniority
Staff · 2+ years exp

Confirmed on the employer's own hiring board on Oct 20, 2026. First seen by Alion on Oct 18, 2026.

Overview
Company
Impact
Profile match

HCLTech

HCLTech is a major Indian multinational information technology (IT) services and consulting company headquartered in Noida, Uttar Pradesh. Spun off from the original HCL Group in 1991, it ranks as one of India's largest technology companies alongside firms like TCS, Infosys, and Wipro.
hcltech.com • HQ: Noida, India • Systems Integrators • IT Consulting & Digital Transformation • IT Outsourcing & Dedicated Teams • 5000+ employees • Est. 1976
Tech stack of HCLTech

Job Summary

  • B.Tech./M.Tech with 2 to 10 years of experience exclusively in DFT.
  • Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
  • Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
  • Spy Glass experience to resolve DFT DRC at RTL stage is a must.
  • Good to have functional & integration knowledge of TAP controllers and JTAG
  • Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.

Good at Communication. Compatible to work with India teams

Key Responsibilities

  • B.Tech./M.Tech with 2 to 10 years of experience exclusively in DFT.
  • Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
  • Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
  • Spy Glass experience to resolve DFT DRC at RTL stage is a must.
  • Good to have functional & integration knowledge of TAP controllers and JTAG
  • Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.

Good at Communication. Compatible to work with India teams

Skill Requirements

Other Requirements

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