Senior Design Lead
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Salary
≈ $28k – $63k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff
Confirmed on the employer's own hiring board on Nov 1, 2026. First seen by Alion on Oct 30, 2026.
Overview
Company
Impact
Profile match
HCLTech is a major Indian multinational information technology (IT) services and consulting company headquartered in Noida, Uttar Pradesh. Spun off from the original HCL Group in 1991, it ranks as one of India's largest technology companies alongside firms like TCS, Infosys, and Wipro.
Job Summary
Own microarchitecture, RTL development and integration for PCIe, ASP and MMC subsystems
Key Responsibilities
Develop synthesizable Verilog/SystemVerilog RTL.
Design/integrate PCIe, processor interfaces, DMA/GDMA, interrupts, NoC, telemetry and control logic.
Drive lint, CDC/RDC, synthesis, LEC and timing readiness.
Debug RTL/DV integration issues and support RTL Freeze/ECO closure.
Skill Requirements
Strong Verilog/SystemVerilog and digital design fundamentals.
PCIe/high-speed interface and AXI/AHB/APB experience.
Hands-on experience with CDC/RDC, lint, synthesis, STA and LEC.
Exposure to SpyGlass, Design Compiler/Genus, PrimeTime and Verdi.
Other Requirements
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