Senior Standard Cell and IP Application Engineer

Job Details:

Job Description:

We are looking for a Senior FIP Enablement and Support Engineer to join the Intel Foundry / DTP Customer Engineering team. The successful candidate brings deep expertise in Foundational IP (Standard Cell Libraries, GPIOs, PLLs, and Analog/Mixed-Signal IPs) and a strong understanding of IP QA, packaging, and release processes across Synopsys and Cadence design flows.

In this role, the engineer will own customer-facing release delivery for Foundational IP, partner with FIP development teams on quality and integration, and serve as a key technical interface for Intel Foundry Services (IFS) ecosystem customers. The role requires sound technical judgment, the ability to navigate ambiguity, and the capacity to drive initiatives independently across multiple stakeholders and organizations.

The candidate will work in close collaboration with Foundry Services teams, ecosystem partners, FIP development teams, and cross-org stakeholders across IPG, IFA, CDA, ADG, and PESG to deliver winning solutions for internal and external customers.

Primary Responsibilities

• Package, validate, and release high-volume Foundational IP collateral (Standard Cell libraries, PDK content, GPIOs, PLLs) to IP delivery portals and PLM systems including IPX, UCM, Teamcenter, and FLPR, meeting customer commit dates and quality targets.
• Drive end-to-end release execution for assigned IP families, including QA monitoring, packaging throughput, and adherence to SDLC/SDL certification requirements and Intel IP governance standards.
• Serve as the primary technical point of contact to internal and external customers for technical analysis, debug, and integration support; liaise with FIP development teams to drive resolution of quality and integration issues.
• Coordinate with Technical Program Managers (TPMs) and customer engineering leads on external release communication, customer-facing documentation, and release notes.
• Review IP performance and quality to ensure conformance with desired standards and targets; contribute to the development of QA flows, verification methodology, and release automation.
• Drive continuous improvement in packaging throughput, release tooling, and customer support workflows (e.g., Jira / JSM-based intake and triage).
• Develop customer-facing collateral, including application notes, white papers, integration guides, and other supporting documentation to improve customer experience and reduce support load.

• Mentor junior engineers and contribute to team-wide best practices in IP release and customer support.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, with 4+ years of relevant industry experience, OR
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, with 3+ years of relevant industry experience. Preferred Qualifications:
• Demonstrated experience in IP Quality Assessment, IP Release processes, and Technical Customer Support using industry-standard tools and methodologies.
• Technical background in IC design, verification, QA, and IP release for advanced process nodes.
• Hands-on experience with Standard Cell Libraries, Analog/Mixed-Signal IPs (PLLs, GPIOs), and library characterization and QA flows.
• Familiarity with foundry PDK release flows and IP Lifecycle Management (PLM) systems such as Teamcenter and Carbon.
• Working knowledge of Synopsys and Cadence design and characterization tools used in standard cell and analog IP flows.
• Experience supporting external foundry customers in an IFS-like ecosystem model is a strong plus. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.