Principal Engineer – CAD Design Engineering & EDA Infrastructure
Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Sep 15, 2026. Lattice Semiconductor scores B on the Alion truth index.
Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
Job Description:
Principal Engineer - CAD Design Engineering & EDA Infrastructure
We are seeking an experienced and highly technical Principal Engineer to lead the strategy, architecture, development, and operational excellence of our CAD and EDA Infrastructure. This role is responsible for enabling world-class semiconductor and hardware design teams through scalable design environments, automation, tool optimization, cloud adoption, and engineering productivity initiatives.
The ideal candidate combines deep expertise in semiconductor design flows, EDA tools, infrastructure engineering, and large-scale automation with strong leadership and cross-functional collaboration skills.
Key Responsibilities
CAD & EDA Infrastructure Leadership
Define and execute the vision, roadmap, and strategy for CAD and EDA infrastructure supporting ASIC, SoC, IP, and verification teams.
Lead the design, deployment, and maintenance of highly scalable and secure engineering environments.
Drive infrastructure modernization initiatives including cloud-enabled design workflows, hybrid compute environments, and next-generation engineering platforms.
Partner with design, verification, implementation, and architecture teams to understand evolving tool and infrastructure requirements.
EDA Tools & Design Flow Development
Optimize RTL-to-GDSII design flows across synthesis, place-and-route, STA, DFT, verification, emulation, and signoff.
Evaluate, deploy, and support industry-standard EDA tools from Synopsys, Cadence, Siemens/Mentor, and other vendors.
Standardize methodologies and best practices across global engineering teams.
Improve tool reliability, performance, and user productivity through automation and workflow optimization.
Automation & Engineering Productivity
Drive automation using Python, Tcl, Perl, Shell scripting, and modern software engineering practices.
Build self-service platforms and dashboards for monitoring tool usage, licenses, compute resources, and design flow metrics.
Reduce design cycle times through process optimization and infrastructure innovation.
Implement CI/CD and DevOps practices for CAD environments and engineering workflows.
Infrastructure & Compute Management
Architect and manage large-scale Linux-based compute farms and distributed job scheduling systems.
Optimize storage, networking, HPC clusters, and cloud resources to support demanding EDA workloads.
Manage EDA license infrastructure, capacity planning, and utilization optimization.
Ensure high availability, reliability, security, and compliance of engineering environments.
Technical Leadership
Serve as a subject matter expert and trusted advisor to design leadership and engineering teams.
Mentor engineers and contribute to the growth of CAD and infrastructure talent.
Influence technology decisions and provide guidance on future engineering platform investments.
Lead root-cause analysis and resolution of complex technical issues impacting engineering productivity.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
12+ years of experience in semiconductor design methodologies, CAD engineering, or EDA infrastructure.
Deep understanding of ASIC/SoC design and verification flows.
Strong expertise with Linux/Unix environments and distributed computing systems.
Hands-on experience with leading EDA platforms from Synopsys, Cadence EDA.
Advanced programming and automation skills in Python, Tcl, Shell, or similar languages.
Experience managing large-scale compute farms, license servers, storage systems, and enterprise infrastructure.
Strong analytical, problem-solving, and stakeholder management skills.
Pay & Benefits
Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.
For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.
Base Pay Range
230732.01In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.
Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.