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Salary
≈ $20k – $51k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff · 5+ years exp

First seen by Alion on Aug 25, 2026.

Overview
Company
Impact
Profile match
LeadSoc Technologies is an Indian semiconductor design services company. Its engineers handle static timing analysis, physical design and synthesis for system-on-chip projects, and its leads handle multi-voltage timing closure, timing correlation between place and route and sign-off, and timing engineering change orders. The company is based in Bengaluru, India.

Job Description :

- Physical Design Implementation and Methodology : Engage in the implementation of physical design, develop methodologies, and manage sign-off processes.

- Core Design Tasks : Execute floorplanning, clock planning, placement and routing, timing closure, and physical verification to ensure design integrity and performance.

- Project Management : Oversee project schedules, troubleshoot design and workflow issues, and drive methodological improvements and execution strategies.

- Collaborative Teamwork : Work collaboratively with team members to successfully complete projects within designated timelines.

- Programming Skills : Utilize programming skills to effectively complete tasks, with a focus on scripting and automation to enhance workflow efficiency.

- Proficiency in EDA Tools : Demonstrate proficiency in using Electronic Design Automation (EDA) tools such as Innovus, ICC2, LEC, PrimeTime, Calibre, among others.

Requirement :

- Experience : 5+ Years Experience.

- Deep Submicron Technology Experience : Hands-on experience with SYN/APR/Signoff and tapeout in deep submicron technology.

- Familiarity with EDA Tools : Proficient in using EDA tools such as ICC, ICCII, and INNOVUS.

- ASIC Flow Knowledge : Well-versed in the ASIC design flow.

- Programming Skills : Proficient in Tcl, Perl, scripting, C, and C++ programming languages.

- Strong Communication Skills : Excellent communication abilities.

- Proactive and Responsible : Highly proactive, enthusiastic, and responsible.

- Large-Scale Design Experience : Experience handling designs with more than 2 million instance counts is preferred.

- Top-Level Physical Design and Advanced Node Experience : Experience in top-level physical design and advanced node tapeout is highly desirable.

Skills

Physical Design, EDA, TCL, Perl, C, C++

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