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Salary
≈ $21k – $52k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff · 5+ years exp

First seen by Alion on Aug 25, 2026.

Overview
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LeadSoc Technologies is an Indian semiconductor design services company. Its engineers handle static timing analysis, physical design and synthesis for system-on-chip projects, and its leads handle multi-voltage timing closure, timing correlation between place and route and sign-off, and timing engineering change orders. The company is based in Bengaluru, India.

Job Title: Lead Synthesis Engineer

Experience: 5 to 12 Years

Location: Bangalore

Requirements:


- 5 years of experience in Synthesis.

- Worked on 7nm/5nm/Future sub-micron Technologies.

- Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.

- Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.

- Familiar with pre-STA timing analysis using Primetime or Tempus.

- Familiar with low power check using Conformal Low Power or VCLP tool.

- Experience in verifying constraints quality and completeness.

- Understanding of UPF & Low power concepts.

- Familiar with functional ECO flow and implementation.

- Familiar with DFT Insertion and debugging basic DFT issues.

- Co-work with RTL, DFT and PD engineers to meet PPA targets.

- Well versed with TCL/Perl/Shell script.

- Self-starter and highly motivated.

- Strong debugging, initiative and analysis/problem solving skills.

- Minimum 4+ years of experience in Synthesis and Physical Synthesis

Skills

Synthesis, Static Timing Analysis, Primetime, RTL, DFT, TCL, Perl

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