DRAM Verification Engineer, Up to Sr. Staff

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General Summary:

Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform high performance AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Job Overview

Qualcomm Custom Memory and STCO Team is seeking a DRAM Verification Engineer at Staff/Senior Staff level to develop and verify next-generation custom DRAM and memory subsystem solutions. You will work closely with architecture, design, and silicon validation teams to ensure functional correctness, performance, and robust verification closure.

What We're Looking For

A hands-on verification engineer who can take ownership of complex memory verification, identify coverage gaps, debug challenging failures, and drive verification to closure

Key Responsibilities

• Develop SystemVerilog/UVM verification environments for DRAM and memory subsystems.
• Create verification plans, constrained-random tests, checkers, scoreboards, SVA assertions, and functional coverage.
• Verify DRAM functionality including read/write, refresh, mode registers, initialization, training, timing, and low-power states.
• Verify memory controller/DRAM interfaces and complex protocol and timing interactions.
• Drive functional, code, and assertion coverage to closure.
• Debug RTL and gate-level simulation failures and support SDF/GLS verification.
• Partner with design, architecture, and silicon teams to reproduce and root-cause pre- and post-silicon issues.

Minimum Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Experience with SystemVerilog and UVM.
• Strong understanding of digital design and verification methodologies.
• Experience with simulation, debugging, assertions, and coverage-driven verification.

Preferred Qualifications

• Experience with DRAM, DDR, LPDDR, HBM, or custom memory architectures.
• Knowledge of DRAM commands, timing, refresh, training, and power management.
• Experience with SVA, formal verification, CDC/RDC, GLS/SDF, or low-power verification.
• Experience with Python, Perl, Tcl, or shell scripting.
• Strong problem-solving, debugging, and communication skills.

Soft Skills:

• Self-Starter with good communication skills and team-working spirit
• Strong problem-solving and analytical skills
• Ability to work independently and as part of a team

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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