Physical Verification Engineer

As a Physical Verification Engineer, you will be responsible for ensuring that complex IC designs comply with foundry design rules and are physically clean for tape-out.

Education Requirements:

Degree: B.E. / B.Tech / M.E. / M.Tech in Electrical Engineering, Electronics & Communication Engineering (ECE), Microelectronics, VLSI Design, or a related technical discipline.

Key Responsibilities:

• Perform full-chip and block-level physical verification checks, including DRC, LVS, ERC, and ANTENNA.
• Debug complex DRC and LVS failures and work closely with Physical Design and Layout teams to resolve violations.
• Run and debug PERC (Programmable Electrical Rule Checking) for reliability and ESD checks.
• Collaborate with foundry teams to understand RuleDeck requirements and run verification using standard EDA tools.
• Drive physical verification run-time optimizations and script repetitive debug flows.

Technical Qualifications:

• Experience: 3+ years in ASIC/SoC Physical Verification.
• Tools: Expert knowledge of Calibre (DRC/LVS/PERC), IC Validator, or Pegasus.
• Nodes: Experience with advanced technology nodes (7nm, 5nm, 3nm preferred).
• Skills: Strong understanding of CMOS layout design, dummy insertion, density rules, and metal fills.
• Scripting: Proficiency in TCL, PERL, or Python for verification automation.

Skills

ASIC, Calibre, IC Validator, Pegasus, Physical Verification, SOC