[2027 Campus Hire] Full Custom Layout Engineer

Fresh graduates who are eager to get involved with industry most advanced semiconductor process technology are a perfect fit for our team. Candidates with strong passion in learning, problem solving, and decision-making skills are welcome to apply.

Candidates will be able to develop in the following area:

- Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow

- Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in debugging DRC/LVS and all other verifications

[What you will do]

- Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones

- Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow

- Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule

- Responsible for in-house IP/library developments

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