Salary
≈ $101k – $228k per year (Estimated)
Location
In office (Irvine)
Confirmed on the employer's own hiring board on Sep 25, 2026. First seen by Alion on May 5, 2026.
Overview
Company
Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
The Interconnect Solutions team is searching for qualified candidates to join our fast-growing team. As a member of this dynamic team, you will work on state-of-the-art next generation electrical and optical transceivers for data centers serving cloud infrastructure as well as the growing field of AI and high-performance computing. We are looking for ambitious analog and mixed-signal designers with exposure to silicon photonics and electro-optic systems who are willing to learn, grow, and contribute to a diverse portfolio of high-speed interconnect products.
- Architecture study and evaluation of advanced high-speed SerDes and optical transceiver topologies targeting 100G/lane PAM4 and beyond, including EIC/PIC partitioning and link-budget definition.
- Design and verification of high-speed, high-performance analog and mixed-signal circuits including, but not limited to: modulator drivers (MRM/MZM/EAM), TIAs, front-end circuits, samplers, comparators, ADCs, DACs, PLLs, CDRs, clock distribution, heater drivers, and bias DACs.
- Electro-optic system modeling and co-simulation with PIC designs, including behavioural modeling of photonic devices (MRM, MZM, EAM, PD, heaters, laser sources) in Verilog-A, MATLAB, or Python.
- Collaborate with package and SI/PI teams to define and sign off EIC-to-PIC interface, bump map, and supply distribution for co-packaged and advanced-packaging contexts.
- Partner with DSP and algorithm teams on TX/RX equalization partitioning (analog CTLE/FFE/DFE vs. digital DSP) and link adaptation.
- Evaluate, measure, and debug silicon with firmware and test teams through bring-up and post-silicon validation until it reaches high-volume production.
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