GPU Design Verification Lead

MediaTek • Processors, MCUs & AI Chips • RF & Wireless Hardware • SystemVerilog • 23 days ago
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Salary
≈ $25k – $57k per year (Estimated)
Location
In office (Hsinchu)
Seniority
Staff

Confirmed on the employer's own hiring board on Oct 17, 2026. First seen by Alion on Aug 2, 2026. MediaTek scores A on the Alion truth index.

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MediaTek

MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
mediatek.com • HQ: Hsinchu, Taiwan • AI Chips & Accelerators • RF & Wireless Hardware • Processors, MCUs & AI Chips • 1001-5000 employees • Est. 1997
Tech stack of MediaTek
• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams.
  • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems.
  • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration.
  • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure.
  • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure.
  • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features.
  • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes.
  • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams.
  • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers.
  • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization.
  • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders.
  • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.
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