Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Nov 6, 2025. MediaTek scores A on the Alion truth index.
- DFT Architecture & Insertion: Define and implement Scan (full-scan, compressor), MBIST, and BSD/JTAG strategies for advanced-node SoCs and chiplet/3D-IC designs; own end-to-end insertion flows with Synopsys / Siemens (Tessent) EDA tools.
- ATPG & Advanced Fault Models: Develop and optimize patterns for stuck-at, transition delay, cell-aware, and path-delay fault models; drive fault coverage closure and DRC-clean pattern delivery.
- Simulation & Verification: Validate DFT logic correctness through gate-level simulation (VCS/Xcelium); resolve DFT rule violations and coverage gaps pre-tapeout.
- Post-Silicon Bring-Up & Test: Lead DFT-related activities across CP / FT / HTOL / HVS -- test-mode validation, scan chain continuity, MBIST execution and repair verification. - Volume Diagnosis & Yield Ramp: Apply scan/
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