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Salary
≈ $14k – $26k per year (Estimated)
Location
In office (Hsinchu)

Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Nov 6, 2025. MediaTek scores A on the Alion truth index.

Overview
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Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
Join MediaTek's "DFT for Advanced Process Platform" team -- your work directly impacts Cloud ASIC reliability and yield at the most advanced process nodes (N4/N3/N2 and beyond).

- DFT Architecture & Insertion: Define and implement Scan (full-scan, compressor), MBIST, and BSD/JTAG strategies for advanced-node SoCs and chiplet/3D-IC designs; own end-to-end insertion flows with Synopsys / Siemens (Tessent) EDA tools.

- ATPG & Advanced Fault Models: Develop and optimize patterns for stuck-at, transition delay, cell-aware, and path-delay fault models; drive fault coverage closure and DRC-clean pattern delivery.

- Simulation & Verification: Validate DFT logic correctness through gate-level simulation (VCS/Xcelium); resolve DFT rule violations and coverage gaps pre-tapeout.

- Post-Silicon Bring-Up & Test: Lead DFT-related activities across CP / FT / HTOL / HVS -- test-mode validation, scan chain continuity, MBIST execution and repair verification. - Volume Diagnosis & Yield Ramp: Apply scan/

#LI-ML2

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