ASIC Engineer, Foundry and IP
Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Oct 2, 2026. Meta scores B on the Alion truth index.
Responsibilities
Analyze and benchmark foundry process offering with physical design teams to identify optimal technologies for product roadmaps Drive early PPA evaluation of foundation IP drops by running preliminary PnR experiments to identify issues and opportunities for improvement Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries with foundry partners and Physical design teams Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows Evaluate, benchmark, and choose third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics Participate in physical implementation, and tape-out of silicon test chips targeted at proving out new foundation IP, custom structures
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience in a foundry team driving PPA analysis and engineering army benchmarking Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints Proven track record of participating in test chip tapeouts. Hands-on experience in owning end to end design and sign-off of partitions on a test chip Expert-level command of design environments like Cadence Virtuoso, HSPICE, Spectre Working knowledge of synthesis, PnR, STA and PDV tools to converge a block on a test chip High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large-scale evaluation pipelines and data analysis MS or PhD in electrical engineering 8+ years of experience driving PPA analysis, selection and optimization of foundational IPs - Standard cells and memory compilers in particular Experience owning test chips as chip lead is preferred Experience driving DTCO optimization with foundry partners and design teams on advanced logic technologies is preferred Experience in bringing multiple sub-5nm, 3nm, or 2nm GAA (Gate-All-Around) complex test chips from initial architecture through to validation