Senior Design Verification Engineer

We are seeking a skilled Design Verification Engineer with 4+ years of experience in IP or SoC-level verification. The ideal candidate must have strong hands-on experience with industry-standard verification methodologies and a proven track record of working with high-speed protocols such as DDR, PCIe, or Ethernet. The candidate should be well-versed in Verilog, SystemVerilog, and UVM.

Responsibilities:

• Develop and execute detailed test plans for IP or SoC verification.
• Build and maintain UVM-based test benches to verify complex digital blocks or subsystems.
• Work closely with design and architecture teams to understand design specifications and derive verification strategies.
• Debug simulation failures, identify root causes, and work with design teams to drive resolutions.
• Develop directed and random test cases to validate functional correctness and corner cases.
• Integrate and verify high-speed protocols like DDR, PCIe, or Ethernet at the IP or SoC level.
• Perform code and functional coverage closure to ensure thorough verification.
• Collaborate with cross-functional teams (RTL, DV, validation, software) for end-to-end verification flow.
• Utilize scripting (Python, Perl, or shell) to automate test environments and regressions.

Requirements:

• 4+ years of hands-on experience in design verification.
• Expertise in at least one of the following protocols: DDR / PCIe / Ethernet.
• Proficiency in Verilog, SystemVerilog, and UVM.
• Strong debugging skills and experience with industry-standard simulators.
• Solid understanding of digital design and verification concepts.