ASIC Design Engineer, High Speed IO

We are now looking for RTL Design engineers for our High Speed IO IP's deployed in Automotive chips. As one of the primary designers, you will be responsible for UFS/Ethernet/PCIE/USB IP's of next generation chips. One should possess strong digital design and verification fundamentals.

What you'll be doing:

• As a designer, be responsible for understanding the specific protocol concepts and features, make architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.
• Own micro-architecture and RTL development of design modules
• Micro-architect features to meet performance, power and area requirements
• Work with HW architects to define critical features
• Partner with verification teams to verify the correctness of implemented features
• Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

What we need to see:

• You should be BTech/MTech in EE, ECE or similar stream, having a proven track record with 2+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
• Knowledge of HSIO standards, protocols and architectures of modern SOC's would be a significant plus
• Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams
• Good debugging, analytical and problem solving skills
• Great interpersonal skills and ability to work as an excellent teammate
• Working exposure with AI tools like Claude and Cursor would be a plus

We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you!

Skills

ASIC, CPU, FPGA, Microcontrollers, RTL, SOC