Senior Digital Design Verification Engineer - Hardware

We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join our diverse team today!

As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a best-in-class team that delivers IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols!

What you’ll be doing:

• Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
• Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long-duration system scenarios. Run regressions, debug and triage failures, and reproduce issues in simulation when needed to support root-cause analysis and resolution.
• Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.
• Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
• Work with architects, digital and analog designers, and pre- and post-silicon verification teams to define verification scope, close coverage, and deliver high-quality IP on schedule.

What we need to see:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
• At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level.
• Hands-on experience with Cadence Palladium or a comparable hardware emulation platform, including environment bring-up, regression execution, failure triage, and debug.
• Strong C/C++ programming skills, with experience developing verification models, test infrastructure, or hardware validation tests.
• Strong SystemVerilog skills and experience building verification environments using UVM.
• Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure.
• Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation.

Ways to stand out from the crowd:

• Direct experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium.
• Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation.
• Experience developing SerDes RNM models and correlating their behavior with analog simulation results or silicon measurements.
• Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training.
• Expertise in high-speed protocols such as PCI Express, USB, or SATA.

You will also be eligible for equity and benefits.

This posting is for an existing vacancy.

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