Principal Layout Engineer

NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.

NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.

This team will include all key engineering disciplines in Design, Architecture, Verification, DfT and Physical Design to produce high performance and quality products.

Working in a fast-paced consumer environment, we are looking for an outstanding lead for our Analog Layout team. This team will include support for MCU and for analog custom products being designed both in Catania but also globally.

Your Responsibilities

• Lead a team of analog layout engineers responsible for the physical design of analog blocks and systems

• Responsible for layout of Analog and RF components in MCU, NFC UWB and BT/BLE products

• Work across multiple process nodes and foundries (140nm to 16 nm, CMOS, BCD, FD-SOI, FinFET … )

• Develop the expertise of the team and drive innovation

• Provide accurate estimates on area, performance and timeline

• Drive the team to meet aggressive schedules without sacrificing quality

• Work closely with analog design engineers to ensure seamless integration of layout and design

• Ensure layouts meet performance, power, and area requirements

• Develop and maintain layout scripts and automation tools

• Collaborate with cross-functional teams, including digital layout, design and verification

• Perform layout verification (DRC, LVS … ) and sign-off

• Deliver physical models (LEF, Libs) to subsystem and IC teams for integration

Your Profile

• MSEE/BSEE or working equivalent
• 10 years’ experience in the layout of analog blocks and systems

• Experience with leading a global team of engineers

• Proven track record in delivering working silicon for high volume products

• Solid fundamentals of transistor level integrated circuits and device physics.

• Knowledge of layout matching and parasitics, latch-up, ESD, etc.

• Rigorous and methodical with good analytical skills for debugging issues in design and on silicon

• Proficiency in analog layout tools, such as Cadence Virtuoso, Siemens Calibre ..

• Knowledge of ESD/Latch up fundamentals

• Experience with signal chain and power design layouts

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