Senior Lead Design Engineer
Job Opportunity:Seekinghighly motivated,energetic,team-orientedIndividual Contributorwilling togo deeper into logicdesignandtake the challenge ofarchitecting anddevelopingComplexIPs/ Subsystemsusing the latest advancedDesign flow methodologies and efficient techniques.
Thepersonwould beworkingcloselywithexperienced and motivated team ofglobal systemsexperts,SoC Designfunctionstoaddress thedesign/architecturalchallenges inthe context of thecomplex IP, Subsystem and overall System level designs,towardsproviding a complete solutionwithend to enddesign flowfrom High Level Specifications toactual design Implementation.
Key Responsibilities
Architectand Designcomplex IP and Subsystems across a range of protocolsrequiredforAutomotive Self Driving Vehicles (ADAS)bothVision and Radar,In-Vehiclenetworks,Gateway Systems, Fail SafeSubsystems(ASIL-D)etc.
Own and Lead IP/ SubsystemfromConcepttillIPDesign and Developmentachievingfinal design performance in integrated system within aggressive, market driven schedules.
Ensure quality adherence during all stages of theIP development cycleandcarry out a thorough analysis of existing processes,recommend and implementthe process improvements to ensure ‘Zero Defect’ designs.
Ability to work well as part of a teamof global and local experts to influence and build technological innovations.
Key Skills
Self starterwith7-13years of experiencetoArchitect and Design complexIPdesign/ Sub-systemwith minimal supervision.
Custom Processor Designs with key DSP functionslike those needed forVision and Radar processing.
Experience inHigh SpeedSerial protocols and associated high speed challenges on controller and PHY for PCIe,USB& MIPI CSI/ DSI.
Understanding of key ExternalMemory interfaceprotocols including DDR4 / LPDDR4,QuadSPIFlash interfaces.
Experience in microcontroller architecture, Cache, protocols like AHB/AMBAAXI.
Experience in automotive protocols like LIN,CAN,Flexray- would beadvantageous.
Extensivehands onknowledge of HDLs(Verilog/VHDL),Scripting languages (Perl,Tcl), C/C++for hardware modeling.
Understanding ofend to endIP development flow including complex CDC, RDCconstructs, IP Synthesis, DFT ATPG coverage.
Work on Testbench andTestplandevelopment closely with the verification team.Addressing ofTestability aspects of the IP/ Subsystemalong with functional requirements would be an advantage.
Hands onwork onpre siliconvalidation usingFPGA/Emulation Boardwould be a significant added advantage.
KeySoftSkills
Proficient skills in both written and verbal communication.Canarticulate well.
Has a sense of Ownership and engages everyone with Trust and Respect.
ShoulddemonstrateEmotional Intelligence and Leadership values withabilityto work well as a part ofteamboth local and remote ormultisite.