Analog Layout Engineer

onsemi • Artificial Intelligence • Information Technology • Bachelor's Degree • Python • Perl • 1 day ago
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Salary
≈ $23k – $54k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Junior · 2+ years exp

Confirmed on the employer's own hiring board on Sep 25, 2026. First seen by Alion on Sep 24, 2026. onsemi scores B on the Alion truth index.

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onsemi

Onsemi is an American semiconductor company that was spun out of Motorola in 1999 and has since narrowed itself from a broad commodity chip supplier into a focused power and sensing business. Its silicon carbide and silicon power devices go into electric vehicle traction inverters, chargers and industrial drives, while its image sensors are used in automotive cameras and industrial vision, and it has deliberately exited lower-margin product lines to concentrate on these markets. Headquartered in Scottsdale, Arizona and listed on Nasdaq, it owns its own silicon carbide substrate manufacturing to secure supply.
onsemi.com • HQ: Scottsdale, United States • Information Technology • Artificial Intelligence • Internet of Things • 1001-5000 employees • Est. 1999

Onsemi is seeking a Senior Analog Layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following

Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)

  • Work on layouts of block/module level for integrated circuits from schematics. Verify using design rules provided by technology and design engineering.
  • Work on layout floor planning of schematic block/module level, power routing, latch-up, ESD layout and area optimization using best layout techniques considering mismatch and process variations.
  • Able to perform DRC, LVS, LVL, LEF generation, ERC, Antenna, Density and EM checks.
  • Working with team members/design engineers for innovative, optimal solutions
  • Using production quality workflow and documentation procedures

Minimum Requirements

BS in Electrical Engineering or related 2 years of experience,

Qualification

  • Experience in delivering high quality analog layout IPs
  • Good understanding of layout fundamentals and best practices
  • Proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports
  • Programming knowledge in SKILL, Perl, and/or Python is a bonus
  • Experience with CADENCE or MENTOR GRAPHICS layout tools
  • Solid understanding of semiconductor manufacturing process and DFM techniques
  • Proficient at debugging/fixing LVS/DRC errors
  • Must be familiar with Cadence Design Environment (CDE) and Unix OS
  • Must have strong communication skills and be a team player
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