Principal Digital Design Engineer
Confirmed on the employer's own hiring board on Nov 3, 2026. First seen by Alion on Nov 2, 2026. onsemi scores B on the Alion truth index.
We are seeking a Principal Digital Design Engineer based in Allen, TX, to own the IO subsystem for onsemi’s microcontroller platform. In this role, you will be responsible for defining, architecting, and delivering a highly configurable IO subsystem that supports a wide range of product requirements across multiple end markets.
This position plays a critical role in enabling platform scalability and product differentiation. The IO subsystem must be flexible, reusable, and optimized for performance, power, and area while supporting a wide range of product requirements.
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system architecture, product lines, DFT, physical design, verification, and software teams. This role requires strong technical execution, cross-functional leadership, and the ability to influence platform direction.
Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products
Define subsystem-level specifications, interfaces, and integration strategy aligned with platform and product requirements
Define and implement parameterized and Python generator-based design approaches, enabling scalable and configurable subsystem instantiation
Drive the creation of automatically generated testbenches and verification environments, leveraging UVM frameworks and AI-assisted techniques
Develop high-quality SystemVerilog RTL, ensuring compatibility with automated generation flows and maintainability at scale
Support synthesis, STA, and timing closure activities to ensure signoff-ready designs
Collaborate with verification, DFT, and physical design teams to achieve first-time right silicon
Apply AI/ML techniques to improve design productivity, including code generation assistance, verification acceleration, and design space exploration
Drive PPA optimization while maintaining configurability and reuse targets
Establish best practices for design automation, code generation, and methodology standardization across the organization
Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
10+ years of experience in digital IC design with strong RTL development background
Expert-level proficiency in SystemVerilog RTL design
Strong experience with Python for design automation and tool development
Solid experience with UVM-based verification methodologies and testbench development
Strong understanding of UPF, synthesis, STA, and timing signoff flows
Experience working with DFT concepts and integration
Strong cross-functional collaboration skills across design, verification, physical design, and product teams