Clock / Power HW Validation Engineer

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General Summary:

Job Description

Roles & Responsibilities:

• Own the E2E bare metal framework validation of Qualcomm mobile/ server/ compute SoC clock and power architectures
• Validation planning - understand design changes, visualize standalone and system level test requirements and scenarios
• Test plan development - clearly document test strategy and dependencies
• Conduct validation strategy and test plan review with all stakeholders - architects, designers, verification engineers, software engineers
• Efficiently collaborate with teams in different time zones - both internal and external
• Automate validation process - development, execution, inference using python, perl, shell
• Develop scalable device drivers, standalone and system tests using C
• Review validation platform schematics to ensure post-Si debug support - might have to work with platform design team
• Use lab instruments - multimeter, oscilloscopes , logic analyzers
• Debug complex issues both on pre-Si and post-Si platforms, provide debug direction

Candidate expectations:

• Mandatory:
  • Bachelor’s degree in engineering (electronics, computer engineering etc.)
  • 2+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)
  • Prior work experience in clock/ power validation
  • Proficient in C, Python
  • Experienced in using lab instruments - multimeter, oscilloscopes , logic analyzers
  • Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based SoCs
  • Very good at problem solving - analytical and debugging skills
• Plus:
  • Prior exposure to below SW skills would add an edge above other applicants:
    • Experience with Cross-Compilers, Linkers and makefiles
    • Understanding of coherency and concurrency in modern SoC architectures
  • Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
  • Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus
  • Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage
  • Should have prior work experience in a cross functional matrix work environment

Minimum Qualifications:

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